module icon(
	input clock, rst,
	input [7:0] loc_x,
	input [7:0] loc_y,
	input [7:0] bot_info,
	input [9:0]	pixel_row, pixel_column,
	output reg [1:0] icon_pixel
);

wire [1:0] icon1,icon2;
wire [9:0] scaled_loc_x, scaled_loc_y,loc1,loc2;
wire [10:0] address_1;//,address_2;
reg [23:0] ck_count=0;
reg tick;

//assign loc1 = (pixel_row[3:0]  - scaled_loc_y[3:0]);
//assign loc2 = (pixel_column[3:0] - scaled_loc_x[3:0]);
assign loc1 = (pixel_row  - scaled_loc_y + 14);
assign loc2 = (pixel_column - scaled_loc_x + 8);
assign scaled_loc_x = (loc_x << 2);
assign scaled_loc_y = (loc_y << 2);

assign address_1 = {3'b000,loc1[4:1],loc2[4:1]};
//assign address_2 = {3'b000,loc1[4:1],loc2[4:1]};

bus_rom rb (
  .clka(clock), // input clka
  .addra(address_1), // input [10 : 0] addra
  .douta(icon1) // output [1 : 0] douta
);

bus_rom rb1 (
  .clka(clock), // input clka
  .addra(address_1), // input [10 : 0] addra
  .douta(icon2) // output [1 : 0] douta
);

always @(posedge clock) begin
	if (0< ck_count <= 23'd6_249_999)
		tick = 1'b1;
	else	
		tick = 0;
	ck_count = ck_count + 1'b1;
end

always @(posedge clock)
begin
	if (rst)
		icon_pixel = 2'b00;
	else
	begin	
		if((loc1>=0 && loc1<32) && (loc2>=0 && loc2<32)) begin
		//if(((pixel_row >= scaled_loc_y-6) && (pixel_row < scaled_loc_y+10)) && ((pixel_column >= scaled_loc_x-6) && (pixel_column < scaled_loc_x + 10)))
		//if(((pixel_row >= scaled_loc_y) && (pixel_row < scaled_loc_y+16)) && ((pixel_column >= scaled_loc_x) && (pixel_column < scaled_loc_x + 16)))
			if(clock)
				icon_pixel = icon2;
			else
				icon_pixel = icon1;
		end
		else
			icon_pixel = 2'b00;
	end 
end 
endmodule 
